The Effect of Different Temperatures on the Growth of CVD SiC Coating

What is the SIC coating?

CVD SiC coating refers to silicon carbide produced through chemical vapor deposition, a vacuum process for high-purity materials. It offers excellent thermal, electrical, and chemical properties, making it ideal for semiconductor applications like etching, MOCVD, Si epitaxial, SiC epitaxial, and rapid thermal processing equipment. This method ensures high uniformity, purity, and process control.

 

The surface temperature of the graphite substrate significantly impacts the CVD-SiC coating process. At high temperatures, intermediate gases desorb and discharge, leaving C and Si to form solid-phase SiC coatings. To study how deposition temperature affects the microscopic morphology and density of the coating, experiments were conducted at 900℃, 1000℃, 1100℃, 1200℃, and 1300℃. Results are shown in Table 3 and Figure 2.

 

 

 

When the deposition temperature is 900℃, all SiC grows into fiber shapes. It can be seen that the diameter of a single fiber is about 3.5μm, and its aspect ratio is about 3 (<10). Moreover, it is composed of countless nano-SiC particles, so it belongs to a polycrystalline SiC structure, which is different from the traditional SiC nanowires and single-crystal SiC whiskers. This fibrous SiC is a structural defect caused by unreasonable process parameters. It can be seen that the structure of this SiC coating is relatively loose, and there are a large number of pores between the fibrous SiC, and the density is very low. Therefore, this temperature is not suitable for the preparation of dense SiC coatings. Usually, fibrous SiC structural defects are caused by too low deposition temperature. At low temperatures, the small molecules adsorbed on the surface of the substrate have low energy and poor migration ability. Therefore, small molecules tend to migrate and grow to the lowest surface free energy of SiC grains (such as the tip of the grain). Continuous directional growth eventually forms fibrous SiC structural defects.

Preparation of CVD SiC Coating:

 

First, the graphite substrate is placed in a high-temperature vacuum furnace and kept at 1500℃ for 1h in an Ar atmosphere for ash removal. Then the graphite block is cut into a block of 15x15x5mm, and the surface of the graphite block is polished with 1200-mesh sandpaper to eliminate the surface pores that affect the deposition of SiC. The treated graphite block is washed with anhydrous ethanol and distilled water, and then placed in an oven at 100℃ for drying. Finally, the graphite substrate is placed in the main temperature zone of the tubular furnace for SiC deposition. The schematic diagram of the chemical vapor deposition system is shown in Figure 1.

The CVD SiC coating was examined by scanning electron microscopy to analyze its particle size and density. The deposition rate was calculated using the formula:
VSiC = (m₂ – m₁) / (S × t) × 100%
where VSiC is the deposition rate, m₂ is the mass of the coated sample (mg), m₁ is the mass of the substrate (mg), S is the surface area of the substrate (mm²), and t is the deposition time (h).

The CVD-SiC process involves the thermal decomposition of MTS at high temperatures, generating small carbon-source molecules (such as CH₃, C₂H₂, and C₂H₄) and silicon-source molecules (such as SiCl₂ and SiCl₃). These molecules are transported to the graphite substrate surface by carrier and diluent gases, where they adsorb and react to form droplets that gradually grow and coalesce. The reaction also produces by-products such as HCl gas.

At 1000 °C, the density of the SiC coating improves significantly. The coating consists mainly of SiC grains around 4 μm in size, but some fibrous SiC defects indicate directional growth and insufficient densification.
At 1100 °C, the coating becomes very dense, with no fibrous defects. It is composed of droplet-shaped SiC particles (5–10 μm in diameter) made up of numerous nano-scale SiC grains. Under mass-transfer control, adsorbed molecules have sufficient energy and time to nucleate and form spherical droplets, which combine tightly into a dense coating.
At 1200 °C, the coating remains dense, but the morphology becomes multi-ridged and the surface rougher.
At 1300 °C, gas-phase nucleation occurs due to rapid MTS decomposition. SiC nucleates before reaching the substrate, forming regular spherical particles (~3 μm) that deposit loosely, resulting in a low-density coating. This temperature is unsuitable for dense SiC coating.

In summary, 1100 °C is the optimal deposition temperature for preparing dense CVD-SiC coatings.

 

 

Figure 3 shows the deposition rate of CVD SiC coatings at different deposition temperatures. As the deposition temperature increases, the deposition rate of the SiC coating gradually decreases. The deposition rate at 900°C is 0.352 mg·h-1/mm2, and the directional growth of the fibers leads to the fastest deposition rate. The deposition rate of the coating with the highest density is 0.179 mg·h-1/mm2. Due to the deposition of some SiC particles, the deposition rate at 1300°C is the lowest, only 0.027 mg·h-1/mm2.   Conclusion: The best CVD deposition temperature is 1100℃. Low temperature promotes the directional growth of SiC, while high temperature causes SiC to produce vapor deposition and result in sparse coating. With the increase of deposition temperature, the deposition rate of CVD SiC coating gradually decreases.

More Posts

Precision Grasp: How Next-Gen Vacuum Chucks Secure Yield in the 8-Inch Wafer Era

As the semiconductor industry transitions to ultra-thin 8-inch wafers, physical substrate handling faces critical yield challenges. Discover how Vetek Semiconductor’s high-precision vacuum chucks leverage advanced engineering, precise flatness, and optimized vacuum distribution to eliminate micro-scratching, prevent wafer warping, and safeguard your fab’s operational efficiency.

The Zero-Particle Mission: Why Sub-5ppm Purity is the Foundation of Advanced Epitaxy

In 2026, as wide-bandgap semiconductors power everything from advanced AI servers to 800V automotive inverters, the margins for error have completely vanished. While chip designers push for higher efficiency, fab engineers face a daily battle against a microscopic enemy: contamination and micro-particles inside the process chamber. During high-temperature epitaxy, the standard of your graphite consumables directly dictates your final wafer defect density.

Maximizing ROI: The Financial Logic of Switching to TaC Coatings

In the competitive semiconductor landscape, the “initial purchase price” is often a misleading metric. For manufacturers scaling up to 8-inch SiC/GaN production, true profitability is found in Total Cost of Ownership (TCO).

At Vetek Semiconductor, we advocate for Tantalum Carbide (TaC) not just as a technical upgrade, but as a strategic financial decision to lower your Cost per Wafer.

Why TaC Coating is a Game-Changer for High-Temp Nitrogen Processes

In the world of semiconductor manufacturing, heat is the enemy of stability. As we move toward larger 8-inch wafers, traditional coatings are reaching their limits.

At Vetek Semiconductor, we’ve found that TaC (Tantalum Carbide) is the ultimate solution for longevity, especially in nitrogen (N2) environments.

Send Us A Message

ru_RURussian

С нетерпением жду вашего контакта с нами

Давай поговорим